In the processes for producing printed boards, LSI substrates and the like that are mounted in various electronic devices, electroconductive metal layers that constitute wirings, electrodes and the like are formed. These electroconductive metal layers have been conventionally formed by using combinations of thin metal film forming processes based on physical deposition methods such as a vapor deposition method and a sputtering method, or chemical deposition methods such as a CVD method, and patterning processes such as photolithography and etching.
Furthermore, along with the higher density of electronic devices in recent years, the number of exemplary applications of multilayer LSI substrates and 3D-ICs that use TSVs (through-silicon vias) is ever increasing. The TSVs used in these are formed by sequentially laminating a barrier layer, a seed layer, and a filling material layer over through-holes (via holes) provided in a substrate. At this time, a physical deposition method or a chemical deposition method is applied to the formation of the various metal layers as well.
However, in the thin metal film forming process described above, physical deposition methods have a problem of poor step coverage, in addition to the necessity of large-sized vacuum apparatuses. The problem of step coverage becomes an obstacle particularly to the application to TSVs. On the other hand, in view of chemical deposition methods, there is a problem that the metal compounds used as raw materials are expensive, and there is a concern about an increase in the thin film production cost since the processes themselves are highly expensive and require high temperatures. Furthermore, although chemical deposition methods exhibit satisfactory step coverage when compared with physical deposition methods, it is difficult in many cases to perform uniform film formation over the bottoms of via holes having high aspect ratios.
Thus, investigations have been conducted on the utilization of a plating method as a method of forming a high quality metal film at low cost. Particularly, more attention is paid to electroless plating, which is a technique intended for producing micronized and complicated metal wirings and is also capable of coping with precision processed products. For example, Patent Document 1 discloses a method of attaching metal catalyst particles of Ag and Pd to a substrate, and performing electroless plating by using these catalyst particles as the nuclei for plating. This method is also applicable to a TSV substrate embedding process.
Furthermore, Patent Document 2 discloses a method of using precious metal particles as catalyst particles for circuit pattern formation. In this method, a predetermined compound is applied on a substrate prior to the adsorption of precious metal particles, thereby a self-assembled monolayer (hereinafter, may be referred to as SAM) is formed, and precious metal fine particles are adsorbed thereon. The SAM is applied in order to adsorb precious metal fine particles at desired locations in a desired pattern on the substrate, and to also maintain a stable adsorption state.